IC manufacturers are employing finer circuit widths, low dielectric constant (low-k) materials, and other technologies to make small and high-speed semiconductor devices. Along with these advancements, the challenges of maintaining yield and throughput have also increased. As far as reliability is concerned, the low-k material near die corners has a crack issue, especially in the sawing process.
A semiconductor wafer typically comprises substantially isolated dies (or chips) separated from each other by scribe lines. Individual dies within the wafer contain circuitry, and the dies are separated by sawing and are individually packaged. Alternately, the individual dies may be packaged in multi-chip modules. In a semiconductor fabrication process, the semiconductor device (e.g., an integrated circuit IC) must be continuously tested at every step so as to maintain and assure device quality. Usually, a testing circuit is simultaneously fabricated on the wafer along with the actual devices. A typical testing method provides several test keys located on the scribe lines between dies that may be electrically coupled to an external terminal through a metal pad. The test keys are selected to test different properties of the wafer, such as threshold voltage, saturation current, gate oxide thickness, or leakage current.
In general, the scribe lines are defined in areas of the multi-layer structure that are without a die pattern and have a width of about 80 to 100 μm depending on the dimensions of the dies manufactured in the wafer. In order to prevent cracks induced during wafer sawing from propagating into the die, each die is usually surrounded by a seal ring of 3 to 10 μm in width. Nevertheless, during wafer manufacture, damage is often introduced because of the scribe lines. Further, when at least one layer of the multi-layer structure is composed of a metal material with a high thermal expansion coefficient, the dimensional variation of the layer is sufficient to introduce high-level internal stress into the wafer in the area of the scribe line. Consequently, portions of the wafer around the scribe line suffer damage, such as peeling, delamination, or dielectric fracture. The types of scribe line damage mentioned above are usually observed when the multi-layer structure includes an inter-metal-dielectric layer of low dielectric constant (low-k).
When considering a design rule for placement of test keys on the scribe line, major consideration is that the stress resulting from the sawing process causes serious peeling near the test keys at the die corners. This results in delamination at the interface between the multiple layers at the die corners. Delamination impacts the reliability of the device, and contributes to production of stringers (residual materials) that interfere with further processing and testing of the integrated circuit.
Several solutions have been proposed to solve some of the technical problems associated with the manufacture and sawing of semiconductor wafers. According to some approaches, grooves are formed in the insulating zone by plasma etching. The formation of these grooves stops many, but not all, cracks from forming. Therefore, a novel test key design rule for preventing delamination or peeling near the die corners is called for.
A conductive ring provided on the main area of the die is well known for providing the wiring that supplies the ground potential or power source potential to circuits in the die. It is not uncommon for stresses to crack a passivation film formed over the die corners during the sealing process of a resin mode package. As disclosed in U.S. Pat. No. 5,371,411, one solution to this problem is to form a slot or row of small holes in the guard ring. However, it is not believed that an array of apertures in the guard ring has been used to prevent a crack or defect generated in an inter-metal-dielectric layer resulting from a die sawing process as proposed by the present invention. If a low-k material is used near the guard ring corners, the crack issue becomes more serious and further reduces reliability. Thus, a novel guard ring design rule at the die corners is also taught by the present invention.